Backed by former Intel CEO Pat Gelsinger, the semiconductor startup wants to solve one of AI's biggest constraints by changing how electricity reaches a processor.
AI's growing demand for electricity has created an opportunity for a startup working on a part of computing infrastructure that rarely attracts public attention: the circuitry that delivers power to a chip.
Powerlattice, based in Vancouver, Washington, has raised $86 million, according to a regulatory filing reported by GeekWire on October 30.
The filing shows the company is seeking $111 million, with 18 investors participating so far. It does not identify the investors or specify the funding round.
Powerlattice declined to comment on the filing.
The financing follows its emergence from stealth in November 2025, when it announced a $25 million Series A co-led by Playground Global and Celesta Capital. At the time, the company had raised $31 million in total.
The startup's backers include former Intel CEO Pat Gelsinger, now a general partner at Playground Global and a member of Powerlattice's board.
Its technology addresses an increasingly expensive problem in AI computing.
Modern AI accelerators require enormous amounts of electrical power. Some emerging processor designs are pushing beyond 2,000 watts per chip, creating challenges for data centers already constrained by electricity and cooling capacity.
But not all of that power reaches the processor efficiently.
Conventional systems deliver electricity through voltage regulators and components positioned outside the processor package.
As current travels through electrical connections, some energy is lost, while rapid fluctuations in demand make it difficult to maintain a stable supply voltage.
Engineers compensate partly by operating with voltage margins that protect processors from sudden power fluctuations.
Those margins can increase energy consumption.
Powerlattice's approach is to move voltage regulation much closer to the processor itself.
The company has developed an integrated voltage regulator, or IVR, chiplet that sits inside the processor package and supplies power directly to the computing silicon.
By shortening the electrical path, Powerlattice aims to reduce energy loss and improve how quickly power delivery responds to changing workloads.
Its Rainier architecture combines miniaturized magnetic inductors, power transistors and control circuits inside a compact component.
Multiple chiplets can also operate together, allowing customers to adapt the design to different GPUs, CPUs and specialized AI accelerators.
Powerlattice claims the architecture can reduce effective computing power requirements by more than 50% while allowing processors to deliver substantially more performance within a fixed power budget.
That is a company-reported technology claim, not an independently verified reduction in total data center electricity consumption.
The distinction matters because a data center also consumes electricity for networking, cooling, storage and other infrastructure.
On October 26, Powerlattice announced that it had demonstrated what it describes as the industry's first monolithic integrated voltage regulator chiplet.
The design combines the controller, power transistors and inductors on a single piece of silicon.
During the demonstration, the chiplet supplied power to a silicon device developed by Powerlattice to simulate the rapidly changing electrical demands of next-generation AI accelerators.
The test was intended to show that the regulator could respond to sudden changes in current while maintaining stable power delivery.
It was not a demonstration of the chiplet operating inside a commercially deployed Nvidia or AMD accelerator.
That remains a significant milestone for the company to achieve.
Powerlattice was founded in 2023 by Peng Zou, Gang Ren and Sujith Dermal, semiconductor veterans with experience at Qualcomm, Intel, Huawei and NUVIA.
NUVIA, a processor design startup acquired by Qualcomm in 2021, employed several engineers who went on to work on advanced computing architectures.
Zou, Powerlattice's CEO, previously held leadership positions in integrated voltage regulator development and holds 15 US patents.
Ren leads engineering, while Dermal oversees systems and customer applications.
The founders are pursuing a business model familiar in the semiconductor industry: develop specialized chip technology that can be incorporated into processors designed by larger manufacturers.
Powerlattice is a fabless company, meaning it does not operate its own semiconductor manufacturing plants.
The company has already developed early silicon and begun providing engineering samples for high-performance processors.
Its next challenge is convincing chip designers to adopt its power delivery architecture in commercial products.
That requires extensive validation, including efficiency testing, thermal reliability, manufacturing compatibility and long-term performance under demanding workloads.
Large processor companies generally make architectural decisions years before products reach the market.
Powerlattice must therefore prove its technology early enough to become part of future chip designs.
The opportunity is substantial. Electricity availability is increasingly determining where AI data centers can be built and how much computing capacity operators can deploy.
If Powerlattice's technology delivers meaningful efficiency improvements at scale, it could help hardware manufacturers extract more computing performance from existing power budgets.
The $86 million disclosed in the filing gives the company additional capital to pursue that objective. Whether the full $111 million offering is completed remains unconfirmed.
Sources: GeekWire on the filing · Monolithic IVR demonstration · Series A · Technology